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Abstract

Deploying deep learning computer vision on extreme edge microcontrollers is heavily constrained by rigid physical bottlenecks, most notably the ~520 KB internal SRAM limit standard to the ESP32 ecosystem. This paper presents a Systematic Literature Review, conforming to PRISMA 2020 guidelines, to evaluate the empirical efficiency frontier of vector-accelerated visual inference on ESP32-class hardware. By synthesizing 47 English-language studies published between 2024 and 2026, this review maps the strict mathematical trade-offs between execution latency, frame rate throughput, and memory allocation. The quantitative data reveals a stark dichotomy in TinyML capabilities. Optimized, lightweight object detection frameworks leveraging INT8 quantization and native SIMD vector instructions achieve exceptional real-time throughput, scaling up to 500 FPS with a 2 ms inference latency. However, these classification models frequently exhaust available SRAM, leaving insufficient overhead for concurrent sensor polling or wireless telemetry in production environments. Furthermore, this synthesis identifies a critical architectural void in on-device pose estimation. Due to the floating-point complexity of coordinate regression, spatial keypoint tracking remains functionally incompatible with current memory limits, suffering from extended latencies (~100 ms) and forcing reliance on host-based processing or physical IMU arrays. Ultimately, this review establishes that while localized bounding-box classification has reached hardware maturity, true untethered keypoint estimation remains a fundamental bottleneck requiring novel hybrid quantization strategies.

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Citation: Sehej Ahuja (2026) Vector-Accelerated Object Detection and Pose Estimation on ESP32 Microcontrollers: A Systematic Literature Review (2024 - 2026). Epistora J. Artif. Intell. & Intell. Syst. 1(1), 1-12. Article EJAIS-107